An n-channel MOS transistor (nMOST) no matter what low or high voltage processes are often used in I/O pads as ESD protection components. However, the contact spiking is a common caused leakage problems which deeply affect the ESD reliability capability of protection devices. Therefore, in this work, we proposed systematic experiments on the drain side: by adding an n-type Well (nWell) structure in the drain area for 0.25-μm low voltage (LV)/ high voltage (HV) processes. After measurement and analysis, it is found that for this LV process adding the nWell in drain side is bad for the It2 robustness of ESD capability, such as the lowest ESD capability condition (S= 9-μm) as compared with the reference group (none with the nWell) is decreased up to 42%, so in the ESD protection application should be avoided to add this structure; in the same token adding the nWell structure in the drain side of an HV nLDMOS, it was found that can expand an ESD current conduction cross-sectional area, which will not dissipate a lot of heat on the surface of the device led to burn, and then enhancing the ESD capability. Meanwhile, the ESD capability of a DUT with S= 9-μm as compared with the reference group (none with the nWell) is increased up to 8%, so adding an nWell structure in the drain side is good for ESD capability (It2 value) of HV MOS devices.